1. Field of the Invention
The present invention relates to an information processing apparatus and, more particularly, to a microprocessor executing a program written not only by a native instruction set but also by a different instruction set from the native set.
2. Description of Prior Art
As a microprocessor has advanced in execution function, there has been proposed and made in practical use a microprocessor operable in not only a native mode for executing a program written by a native instruction set, but also in an emulation mode for executing a program having another instruction set which is basically used for operation of another microprocessor. Such a microprocessor has a mode flag for designating the operating mode. This flag constitutes of a part of a program status word register (PSW). When the mode flag is set to logic "1", for example, the microprocessor operates in the native mode. On the other hand, in case of the mode flag being reset to logic "0", the microprocessor operates in the emulation mode. Since the switching in the operating mode means a change in a task environment, it dealt with in an interrupt process. More specifically, when the microprocessor encounters a mode switching instruction from one of the native and emulation modes to the other thereof, the current contents of a program counter (PC), a program status word register (PSW) and a general purpose register (GPR) are saved in a data memory and a branch processing to a vector address is then performed. The content of the mode flag is changed to the designated mode, so that the program for the designated mode is executed. When the execution of the program is completed, the saved contents are returned to PC, PSW and GPR, respectively, to restart the program of the other mode.
In the microprocessor mentioned above, when an interrupt request is externally issued from a peripheral I/O unit to the microprocessor, the mode flag is forcibly set to one of logic "1" and logic "0". When the microprocessor receives the interrupt request, it saves the current contents of PC, PSW and GPR in the data memory and loads the starting address of the interrupt program to PC. The interrupt program routine is thereby initiated. At this time, assuming that the mode flag is forcibly set to logic "1", i.e. the native mode, the microprocessor is brought into the condition in which the interrupt program is executed in the native mode. This means that the interrupt program is restricted to be written by the native instruction set. On the other hand, it is required that the interrupt program is also executed not only in the native mode but also in the emulation mode. For this purpose, the mode switching instruction from the native mode to the emulation mode is provided at the beginning of the emulation mode interrupt program. As described hereinbefore, the microprocessor deals with the mode switching operation in an interrupt handling manner. That is, by executing the mode switching instruction, the contents of PC, PSW and GPR are again saved in the data memory and the vector address information is loaded to PC. The mode flag is reset to logic "0" to designate the emulation mode. When the emulation mode interrupt program is completed, a return instruction is executed to restore the last saved contents in PC, PSW and GPR. The mode flag is thereby set to logic "1". A return instruction is again executed to restore the saved contents for the suspended program in PC, PSW and GPR.
Thus, in order to execute an interrupt program of the emulation mode, the saving and restoring of the contents of PC, PSW and GPR are performed twice, respectively. In particular, the overhead for the second saving and restoring deteriorates the respondence for the interrupt request and the execution efficiency of the microprocessor.